1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a semiconductor device that includes a semiconductor chip having a plurality of memory cells for storing binary data as polarization states of a ferroelectric.
2. Description of the Related Art
FeRAM (Ferroelectric Random Access Memory) is known as the so-called ferroelectric memory. For example, the FeRAM can have a (2 transistor-2 capacitor)/1 bit structure (simply referred to hereinbelow as 2T2C structure). The FeRAM with the 2T2C structure is a FeRAM for storing one binary data in two memory cells, that is, in two transistors and two capacitors.
A ferroelectric memory (semiconductor chip) and a method for manufacture thereof are disclosed in, for example, Japanese Patent Kokai (Laid-open Application) No. 9-64291. The difference in physical and chemical properties between two interfaces, namely, an interface between a ferroelectric film and an upper electrode provided on the ferroelectric film and an interface between the ferroelectric film and the lower electrode provided below the ferroelectric film, is eliminated by conducting two heat treatments in the process for the manufacture of a memory element. If the difference in physical and chemical properties between these two interfaces is eliminated, it is possible to stabilize the operation of reading data from a memory cell and the operation of writing data into the memory cell because the symmetry of the hysteresis curve of a ferroelectric capacitor is improved.
Japanese Patent Kokai No. 2002-93194 discloses a process of inspecting a ferroelectric memory. In the so-called burn-in inspection process for screening the initial defects in the memory cells having ferroelectric capacitors, the occurrence of imprint effect is prevented by conducting a process of alternately writing “1” data and “0” data into individual memory cells in at least the temperature decrease period of the temperature increase period and temperature decrease period. If the imprint effect is prevented, it is possible to stop deterioration of the memory cells.
The relation between the imprint effect and memory cell deterioration will be described below with reference to FIGS. 10A–10C and FIGS. 11A–11B of the accompanying drawings.
FIGS. 10A–10C are conceptual graphs for explaining the state transition (change in hysteresis characteristic) of a ferroelectric capacitor provided in a ferroelectric memory. The hysteresis characteristic is shown by a dot line, and the hysteresis characteristic after the shift is shown by a solid line. The deterioration of the polarization quantity by the so-called depolarization is shown by a dash-dot line.
FIG. 10A shows a hysteresis characteristic which is considered ideal for the conventional ferroelectric memory. FIGS. 10B and 10C show the hysteresis characteristics that shift from the ideal curve due to occurrence of the imprint effect in the ferroelectric capacitor. A voltage, V (volts), is plotted against the abscissa, and polarization Pr (μC/cm2) is plotted against the ordinate.
In this specification, the “0” data is the binary data which are written into a ferroelectric memory or read therefrom, and which is read at a potential level lower than the reference potential (VREF) level during data reading. The “1” data is a data which is read at a potential level higher than the reference potential (VREF) level during data reading.
FIGS. 11A and 11B are the graphs for explaining the shift with time in a memory cell (ferroelectric capacitor) when the memory cell holds the “0” or “1” data for a long time. Specifically, FIG. 11A schematically illustrates the amount of shift with time of a hysteresis characteristic in a memory cell that has been continuously storing the “1” data (graph I) or “0” data (graph II). FIG. 11B schematically illustrates the shift with time of a read potential with respect to the reference potential (VREF) of a ferroelectric memory. The graph III in FIG. 11B shows the changes in the read potential in a memory cell that stores the “1” data, and the graph IV shows the changes in the read potential in the memory cell that stores the “0” data.
As shown in FIGS. 10A, 10B, and 10C, the relationship between the voltage, V, and polarization, Pr, can be explained by the so-called hysteresis curve.
As understood from FIG. 10A, the hysteresis characteristic curve of a ferroelectric capacitor that has not shifted has a symmetrical shape with respect to the ordinate and abscissa for both the applied potential and the polarization quantity. The potential read from the ferroelectric capacitor in such a state is V0 in case of the “0” data and V1 in case of the “1” data.
As seen in FIG. 10B, the hysteresis curve in case of continuous holding of the “0” data for a long time shifts in the minus direction of the abscissa (voltage), that is, to the left, while maintaining its shape as a whole.
The read potential V0 in FIG. 10B is almost identical to the V0 in FIG. 10A, and the read potential V1 in FIG. 10B seems to be only slightly less than the V1 shown in FIG. 10A. Thus, the ferroelectric memory having the left-shifted hysteresis curve is able to operate with practically no problem.
As shown in FIG. 10C, the hysteresis curve observed when the “1” data is held for a long time shifts in the plus direction of the abscissa (voltage), that is, to the right, while maintaining its shape as a whole.
The difference between the read potentials V0 and V1 in FIG. 10C is much less than that shown in FIG. 10A and FIG. 10B. In a ferroelectric memory, data cannot be read if the difference between the potentials V0 and V1 is small. Thus, it can be understood that there is a high risk of impeding the operation of a ferroelectric capacitor if the hysteresis curve of the ferroelectric capacitor shifts in the plus direction of the abscissa (voltage axis), that is, to the right, by holding the “1” data for a long time.
A semiconductor device having a ferroelectric memory undergo a wafer process, a wafer test, an assembling process, an assembled product test, mounting of the product on a substrate, and a final test before they are shipped.
Those processes and tests inevitably include heating treatments at a high temperature. For example, in the assembling process, heating at a temperature of about 200° C. is carried out during wire bonding and sealing. In the mounting process, heating at a temperature of about 240° C. is carried out in the reflow process.
In the wafer test, the manufactured ferroelectric memory is subjected to an electric characteristic test with a high voltage, an endurance test involving a random number of operations, and a test for inspecting the effect of temperature on characteristics in which the operation is monitored under temperature conditions higher than the usual usage temperature.
In the assembling process and mounting process, thermal stresses are applied to the ferroelectric memory which holds the “0” or “1” data because the “0” or “1” data is written in the ferroelectric memory in the wafer test.
In a ferroelectric memory, the amount of shift of the hysteresis curve increases with time as shown in FIG. 11A, and the polarization quantity of the ferroelectric capacitor (i.e., the read potential) decreases with time as shown in FIG. 11B. The memory life limit is reached when the amplification of read potential by the sense amplifier (SA) becomes impossible due to the decrease in read potential. The hysteresis curve represents the characteristic of the ferroelectric memory.
The above-described imprint effect of a ferroelectric memory and the decrease in polarization quantity (depolarization) of a ferroelectric capacitor are accelerated by thermal stresses applied in the process for the manufacture of the ferroelectric memory and semiconductor device. Thus, the hysteresis characteristic of a memory cell has already shifted and the memory life has already been shortened to the extent of this shift at the time of product shipping. The shortening of service life is especially significant when the hysteresis curve has shifted to the right.
Japanese Patent Kokai No. 9-64291 teaches that the read potential can be stabilized by improving the symmetry of hysteresis curve. However, Japanese Patent Kokai No. 9-64291 does not mention the shortening of the memory cell life by heat treatment, and does not teach any measures for resolving this problem.
Japanese Patent Kokai No. 2002-93194 teaches that shortening of the memory life can be prevented by initializing the hysteresis characteristic at the time of product shipping so as to inhibit the occurrence of the imprint effect at the time of shipping. However, Japanese Patent Kokai No. 2002-93194 does not teach anything about substantive extension of memory life (not prevention of shortening of the life, but extension of the life).
Therefore, there is no technology for realizing service life extension of ferromagnetic memories.